Integrated circuits may be formed on a semiconductor substrate, such as a silicon wafer or other semiconducting material. In general, layers of various materials which are either semiconducting, conducting or insulating are patterned to form components of the integrated circuits. By way of example, the various materials are doped, ion implanted, deposited, etched, grown, etc., using various processes.
Photolithography is commonly utilized during integrated circuit fabrication. Photolithography comprises patterning of photoresist by exposing the photoresist to a pattern of actinic energy, and subsequently developing the photoresist. The patterned photoresist may then be used as a mask, and a pattern may be transferred from the photolithographically-patterned photoresist to underlying materials.
A continuing goal in semiconductor processing is to reduce the size of individual electronic components, and to thereby enable smaller and denser integrated circuitry. A concept commonly referred to as “pitch” can be used to quantify the density of an integrated circuit pattern. Pitch may be defined as the distance between an identical point in two neighboring features of a repeating pattern. Due to factors such as optics and actinic radiation wavelength, a photolithographic technique will tend to have a minimum pitch below which the particular photolithographic technique cannot reliably form features. Thus, minimum pitches associated with photolithographic techniques present obstacles to continued feature size reduction in integrated circuit fabrication.
Pitch multiplication, such as pitch doubling, is one proposed method for extending the capabilities of photolithographic techniques beyond their minimum pitch. Pitch multiplication refers to methodologies which reduce pitch relative to a starting pitch of a photoresist template. For instance, a pitch-doubling process is a process which forms a mask having a pitch that is about one-half of the pitch of the starting photoresist template.
Pitch multiplication methodology may involve forming features narrower than minimum photolithographic resolution by depositing layers to have a lateral thickness which is less than that of the minimum capable photolithographic feature size. The layers may be anisotropically etched to form sub-lithographic features. The sub-lithographic features may then be used as a patterned mask. For instance, the sub-lithographic features may be used for integrated circuit fabrication to create higher density circuit patterns than can be achieved with conventional photolithographic processing.
It is desired to develop new methodologies for pitch multiplication, and to develop processes for applying such methodologies to integrated circuit fabrication.